Delete comment from: Ken Shirriff's blog
Metastability is rare, because for it to occur, the relative timing between the data and the clock needs to hit an extremely shot duration vulnerable window. But there is a simple trick to produce metastable behavior on purpose. I think there was an app note, possibly by Jim Williams, explaining this technique.
In a nutshell, the ideas is as follows. Suppose we we have a D-type flip-flop, and the input data transitions low to high around the vulnerable interval. Then, if the transition occurs too early, one is latched in, and if the transition is too late, a zero is latched in, and when the transition occurs right in the middle, we get the metastable state.
So what we do, we low-pass filter the output signal, and feed it back into a voltage-controlled delay line for the data input. The controlled RC delay can be made by using junction capacitance of a reverse-biased diode -- the greater the voltage the lower the capacitance, the lower the delay.
Of course the circuit and the clock both have to be reasonably low-noise in order for this to work correctly, and the demonstration would be easier with the older, slower logic families.
Aug 29, 2025, 1:51:33 AM
Posted to Here be dragons: Preventing static damage, latchup, and metastability in the 386