tag:blogger.com,1999:blog-7033598.post-19602234558707697832008-03-12T22:01:00.000-07:002008-03-12T22:04:41.332-07:00Clock divider is widely used in the digital design. The following is a summary of this cliche topic:<br /><br />(1) divide by an even number (n = 2k)<br />A simple counter will do it<br /><br />(2) divide by an odd number (n = 2k + 1)<br />If apply a counter that only triggers on rising clock edge, 50% duty cycle can not be obtained. To maintain 50%, the counter has to be triggered on both rising dege and falling edge<br /><br />(3) divide by fractional n = (2k + 1 ) / 2<br />The same "triggering on both edge" idea applies here. Triggering on both edge is close to double the clock frequency. To do this in Verilog, two "always" statement can be used. One is hinged on rising edge and the other is on falling edge. Each always statement can produce one pulse train with correct phase and the two pulse trains can be OR-ed together to achieve the goal. 50% duty cycle is obtainable in this special case.<br /><br />(4) divide by m/n, (m, n) = 1, m > n > 2<br />It is next to impossible to get 50 % duty cycle. And jitter is also unavoidable. A counter with step n and wrapping at m or (m/2) might be considered.HAx4http://www.blogger.com/profile/07815763128733150479noreply@blogger.com