Eric's Blog for work

tag:blogger.com,1999:blog-296409832009-07-12T09:51:35.800+08:00Eric's Blog for workDigital IC design,Verification,FPGA,Video Codec...Eric YanEric0208@gmail.comBlogger78125tag:blogger.com,1999:blog-29640983.post-7693311917859395142009-05-10T22:47:00.001+08:002009-05-10T22:52:37.242+08:00linux防止误删除的简单办法[Tips]

建立硬链接，ln 源文件【链接名】硬链接的作用就是允许一个文件拥有多个有效路径名，直到删除最后一个链接文件才会真正被删除

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-71488041793813989532009-04-30T22:39:00.000+08:002009-05-10T22:52:18.126+08:00Dirac-> vc-2 ?

About DiracDirac is an advanced royalty-free video compression format designed for a wide range of uses, from delivering low-resolution web content to broadcasting HD and beyond, to near-lossless studio editing. The Dirac ProjectOriginally created by the BBC Research department, the Dirac project has expanded to include companies providing hardware equipment and software for handling Dirac

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-66608652407425722312009-03-24T21:25:00.001+08:002009-03-24T21:25:27.979+08:00硅谷模式未必适合本土创业公司【转自老杳吧】

本人目前就职于一家本土集成电路创业公司，对这篇文章高度认同。所谓硅谷集成电路创业模式一般包含三个阶段，一、获得VC对创意及团队认可，一般集成电路设计创业团队可以获得100-500万美元的启动资金创业；二、产品开发完成后创业公司会二次融资，额度一般在500-2000万美元用于产品推广；三、技术或产品获得市场认可后创业公司一般会选择直接IPO或被知名跨国公司收购，成功的硅谷创业公司一般都会经历上述三个阶段。与硅谷模式不同，集成电路在中国发展几十年，上市的只有中星微、展讯和珠海炬力，能够被跨国公司收购的案例很少，十年前新涛科技被IDT以8500万美元收购以及上海掌微被Sirf 1.25亿美元收购之外鲜有成功，其实这两家也不能算是本土创业公司，总部都在硅谷，运营主体都设在美国，中国只设有部分研发，甚至所销售的产品也是以海外为主。硅谷创业以核心技术为目标，能被跨国公司收购很正常，

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-60811715283661916282008-12-25T20:58:00.001+08:002009-05-10T22:52:52.894+08:002009 Coming

Merry Christmas & Happy New Year!

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-55760749406143895742008-12-24T20:49:00.002+08:002008-12-25T19:56:39.494+08:00diff in linux

diff在linux下用来比较两个文件或者文件夹的内容，具体使用可以参考http://linux.about.com/library/cmd/blcmdl1_diff.htm，其中-b可以比较不同类型的文件，如dos，unix，但经实践证明，如果两个文件类型不一样，且文件比较大，如大于1MB时，比较时间会很长，why? 如果我们把Windows下产生的文件在linux下执行一次dos2unix，转换成unix类型，然后再用diff比较，时间将大大减少。仅试过文本文件。

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-53997829338361453332008-11-08T23:02:00.008+08:002008-11-09T00:01:23.509+08:00Virtex5 DSP48E Synplify8.6.2 bug?

最近工作中遇到的一个问题，不知道是否是工具的bug，在此备案。问题描述：设计中所用到的一个乘法器，在fpga验证时不能工作，用逻辑分析仪查看得知乘法器输入正确，但输出有问题。通过多次修改并用综合后的网表仿真得知是synplify在综合时调用DSP48E时处理出错，具体分析如下：环境：Xilinx的Virtex5 LX系列FPGA，Synplify8.6.2综合，ISE9.2实现，Modelsim后仿设计背景：乘法器的输入，一端为寄存器直接输出，另一端是比较复杂的组合逻辑，输出结果再做加法等运算，然后送入寄存器。DSP48E简介：Virtex-5 DSP48E Slice 包含 Virtex-4 DSP48 的所有功能以及多种新功能。这些新功能包括一个更宽的 25 x 18 乘法器和一个扩展后用作逻辑单元的加/ 减功能。看框图：其中输入可以有两级寄存器，

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-60884739804231397942008-09-30T08:42:00.001+08:002008-11-09T00:01:30.864+08:00IPcore Release Package

IPcore Release Package Should include:Synthesizable Verilog RTLBit-accurate C modelVerilog testbench Detailed product documentationDesign specificationsIntegration guidelinesComplete verification suiteVHS tape with example noisy signalsExtensive tests including corner-case scenarios Golden test result vectorsFPGA test board (with testbench and supporting files)Support and trainingto be added...

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-71999430313172474562008-09-29T08:34:00.001+08:002008-11-09T00:01:41.801+08:00清除所有.svn目录

一、在linux下删除这些目录是很简单的，命令如下find . -type d -name ".svn"|xargs rm -rf或者find . -type d -iname ".svn" -exec rm -rf {} \; 全部搞定。二、在windows下1、在项目平级的目录，执行dos命令： xcopy project_dir project_dir_1 /s /i2、或者在项目根目录执行以下dos命令 for /r . %%a in (.) do @if exist "%%a\.svn" rd /s /q "%%a\.svn"3、直接用windows的搜索功能，打开搜索隐藏文件的选项，然后搜索.svn，再一起删除即可

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-67463838585998156172008-09-27T19:59:00.002+08:002008-09-27T20:05:58.723+08:00Power Savings Techniques

From snug San Jose -- Power Analysis MethodologyFrom Spreadsheet to Sign-off by George Cuan, Cisco Systems, Inc.

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-46131070878161229512008-08-31T22:53:00.001+08:002008-09-27T20:07:00.897+08:00async fifo design

Key points:1. fifo body: dual ports sram or registers array2. read and write address for sram3. empty and full flag for the fifo body, it's the most important, and there are two methods presented in the reference paper. 4. almost empty or almost full flag, if needed5. fifo content depth or fifo space depth, if needed6. some special case for the special application, eg. the predicable r/w clock

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-51197863627141418232008-06-05T11:03:00.001+08:002008-09-27T20:08:30.090+08:00H.264 Baseline Decoder from opencores

Nova is a low-power realtime H.264/AVC baseline decoder of QCIF resolution, targeting mobile applications. It is a dedicated, full hardwired and self-contained ASIC design without utilizing any GPP/DSP cores. It has been successfully verified on Xilinx Virtex-4 FPGA and 0.18um ASIC chip. The measured power consumption is 293uW@1V for 30fps QCIF decoding. Introduction page:http://

Eric YanEric0208@gmail.com4tag:blogger.com,1999:blog-29640983.post-56107340090629518902008-05-28T22:20:00.001+08:002008-09-27T20:07:09.556+08:00Berkeley University EECS Course WEB Sites

http://inst.eecs.berkeley.edu/classes-eecs.html There are many EE classes online, so good for the EE students and RDs. EECS1 Introduction to EECSEECSBA1 Strategic Computing and Communications TechnologyEECS20N Structure and Interpretation of Systems and SignalsEE24 Freshman SeminarEE40 Introduction to Microelectronic Circuits EE42 Introduction to Digital ElectronicsEE43 Introductory Electronics

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-52726501463232807002008-05-22T20:28:00.002+08:002008-05-25T10:43:41.853+08:00Support earthquake relief in China

From:http://en.wikipedia.org/wiki/2008_Sichuan_earthquakeThe 2008 Sichuan earthquake (Chinese: 四川大地震), which measured at 8.0 Ms according to the China Seismological Bureau, and 7.9 Mw according to USGS, occurred at 14:28:01.42 CST (06:28:01.42 UTC) on 12 May 2008 in Sichuan province of China. It was also known as the Wenchuan earthquake (Chinese: 汶川大地震), after the earthquake's epicenter in

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-59909103109751761552008-03-23T12:47:00.002+08:002008-03-23T12:59:52.013+08:00新的虚拟主机

最近新申请了国外的虚拟主机，以后blogger的ftp发布顺畅多了。庆祝...

Eric YanEric0208@gmail.com1tag:blogger.com,1999:blog-29640983.post-31600151025079019372008-03-10T21:04:00.001+08:002008-03-10T21:09:48.720+08:00registered output

最近项目碰到的一个问题，设计时没用寄存器输出，导致接口部分由于时序问题出错。就此问题谈点自己的看法。一般来说，我们只是在芯片的接口处考虑寄存器输出，因为内部逻辑都能在EDA工具的控制较好地保证timing，但接口处由于对方的逻辑未知，无法保证timing，在某些case可能会出现timing出错的问题。当项目较大时，综合不能完全top-down，此时在IP的顶层最好也用寄存器输出，以简化IP间接口timing的check。 IP内部的话，不一定非得寄存器输出不可。很多初学者为了简单起见，只要是输出都加上寄存器，这样会浪费面积，而且有时电路的效率也会降低（delay1T）。总的来说，是否需要寄存器输出虽是个小问题，但对于高效稳定的设计，任何小问题都不得放过。

Eric YanEric0208@gmail.com1tag:blogger.com,1999:blog-29640983.post-88240716319807138122008-01-17T20:10:00.000+08:002008-01-17T20:24:41.253+08:00How to do Statistical Timing Analysis for a Path that Includes Clock-shaping Circuit

Question:I have a pulse-shaping circuit similar to the one shown in the following figure.In the following circuit, only the falling edge from and1/A and rising edge fromand1/B should be used (see waveforms).How should this be modelled in PrimeTime?Answer:This can be done using the set_case_analysis command and assigning values "falling"to and1/A and "rising" for and1/B. A sample verilog netlist,

Eric YanEric0208@gmail.com1tag:blogger.com,1999:blog-29640983.post-34033295605556866702007-12-31T21:37:00.001+08:002007-12-31T22:32:08.614+08:00some video ebook links

1.Title: Video Codec Design: Developing Image and Video Compression Systems Author: Iain Richardson ISBN: 0471485535 http://rapidshare.com/files/21088581/110_0471485535_Video.rar Password: free4vn.org 2.Title: Video Demystified, Fourth Edition (Demystifying Technology) Author: Keith Jack ISBN: 0750678224 http://rapidshare.com/files/21081509/303_0750678224_JACK__K.__2001_._Video_Demystified_-_

Eric YanEric0208@gmail.com2tag:blogger.com,1999:blog-29640983.post-85663661017966871392007-12-24T08:44:00.001+08:002007-12-31T22:31:30.331+08:00Merry Christmas and Happy New Year

Merry Christmas and Happy New Year!

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-60101608573150311012007-12-13T13:35:00.001+08:002007-12-18T22:54:06.464+08:00IC封装

芯片设计规划时要考虑到一个重要因素---封装。 [转载]来源：PCB 技术作者：sjb21ic1、BGA(ball grid array) 球形触点陈列，表面贴装型封装之一。在印刷基板的背面按陈列方式制作出球形凸点用以代替引脚，在印刷基板的正面装配LSI 芯片，然后用模压树脂或灌封方法进行密封。也称为凸点陈列载体(PAC) 。引脚可超过200，是多引脚LSI 用的一种封装。封装本体也可做得比QFP(四侧引脚扁平封装)小。例如，引脚中心距为 1.5mm 的360 引脚 BGA 仅为 31mm 见方；而引脚中心距为0.5mm 的304 引脚QFP 为40mm 见方。而且BGA 不用担心QFP 那样的引脚变形问题。该封装是美国 Motorola 公司开发的，首先在便携式电话等设备中被采用，今后在美国有可能在个人计算机中普及。最初，BGA 的引脚 (凸点)中心距为

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-78907769509942715942007-12-11T23:40:00.001+08:002008-02-15T16:15:23.803+08:00Ebook--Low Power Methodology Manual[printable]

Ebook share, Thanks to visit my blog!Low Power MethodologyManual For System-on-Chip Design.sorry, I can not share this book for some jural reason.if you are interesting with this book, you can refer http://www.synopsys.com/partners/arm/lpmm/lpmm.html

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-74556099239033565572007-12-06T09:23:00.001+08:002007-12-08T13:33:39.427+08:00ECO Flow[By Nir Dahan]

I have posted a blog about ECO some monthes ago, see http://www.yanzhi.org/blog/2007/04/eco.html And now it's another eco post from: Adventures in ASIC Digital Design , just for reference.ECO Flow By Nir Dahan Here is a useful checklist you should use when doing your ECOs. 1. RTL bug fix Correct your bug in RTL, run simulations for the specific test cases and some your general

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-5954389346190531322007-12-01T09:53:00.001+08:002007-12-01T09:55:28.778+08:00What is the difference between hard macro, firm macro and soft macro?

From http://vlsifaq.blogspot.com/ By murali What are IPs? Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-18540614368975986602007-11-21T13:23:00.001+08:002007-12-01T10:01:46.835+08:00Physical Design Flow

from ASIC-System On Chip (SoC)-VLSI Design by muraliLibrariesInputs–outputs from physical design processFloor PlanningPower PlanningTiming Analysis in Physical DesignPlacementClock Tree Synthesis (CTS)Routing

Eric YanEric0208@gmail.com0tag:blogger.com,1999:blog-29640983.post-79925609311258249262007-11-21T10:01:00.001+08:002007-11-21T15:21:49.932+08:00删除文本文件中包含特定字符串所在行[script tips]

grep-v, --invert-match select non-matching linesgrep -v "string" tee tmp.filemv -f tmp.file original.fileOrvi:g/string/d

Eric YanEric0208@gmail.com1tag:blogger.com,1999:blog-29640983.post-41514156853467238442007-11-20T16:25:00.001+08:002007-12-01T10:03:22.320+08:00[转]What is the difference between FPGA and ASIC?

from VLSI Interview Questions by muraliThis question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.FPGA vs. ASIC Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and

Eric YanEric0208@gmail.com0