Eric's Blog for work

新的虚拟主机

2008-03-23T12:47:00.002+08:00

最近新申请了国外的虚拟主机，以后blogger的ftp发布顺畅多了。庆祝...

registered output

2008-03-10T21:04:00.001+08:00

最近项目碰到的一个问题，设计时没用寄存器输出，导致接口部分由于时序问题出错。就此问题谈点自己的看法。一般来说，我们只是在芯片的接口处考虑寄存器输出，因为内部逻辑都能在EDA工具的控制较好地保证timing，但接口处由于对方的逻辑未知，无法保证timing，在某些case可能会出现timing出错的问题。当项目较大时，综合不能完全top-down，此时在IP的顶层最好也用寄存器输出，以简化IP间接口timing的check。 IP内部的话，不一定非得寄存器输出不可。很多初学者为了简单起见，只要是输出都加上寄存器，这样会浪费面积，而且有时电路的效率也会降低（delay1T）。总的来说，是否需要寄存器输出虽是个小问题，但对于高效稳定的设计，任何小问题都不得放过。

How to do Statistical Timing Analysis for a Path that Includes Clock-shaping Circuit

2008-01-17T20:10:00.000+08:00

Question: I have a pulse-shaping circuit similar to the one shown in the following figure. In the following circuit, only the falling edge from and1/A and rising edge from and1/B should be used (see waveforms). How should this be modelled in PrimeTime? Answer: This can be done using the set_case_analysis command and assigning values "falling" to and1/A and "rising" for and1/B. A sample verilog

some video ebook links

2007-12-31T21:37:00.001+08:00

1.Title: Video Codec Design: Developing Image and Video Compression Systems Author: Iain Richardson ISBN: 0471485535 http://rapidshare.com/files/21088581/110_0471485535_Video.rar Password: free4vn.org 2.Title: Video Demystified, Fourth Edition (Demystifying Technology) Author: Keith Jack ISBN: 0750678224 http://rapidshare.com/files/21081509/ 303_0750678224_JACK__K.__2001_._

Merry Christmas and Happy New Year

2007-12-24T08:44:00.001+08:00

Merry Christmas and Happy New Year!

IC封装

2007-12-13T13:35:00.001+08:00

芯片设计规划时要考虑到一个重要因素---封装。 [转载]来源：PCB 技术作者：sjb21ic1、BGA(ball grid array) 球形触点陈列，表面贴装型封装之一。在印刷基板的背面按陈列方式制作出球形凸点用以代替引脚，在印刷基板的正面装配LSI 芯片，然后用模压树脂或灌封方法进行密封。也称为凸点陈列载体(PAC) 。引脚可超过200，是多引脚LSI 用的一种封装。封装本体也可做得比QFP(四侧引脚扁平封装)小。例如，引脚中心距为 1.5mm 的360 引脚 BGA 仅为 31mm 见方；而引脚中心距为0.5mm 的304 引脚QFP 为40mm 见方。而且BGA 不用担心QFP 那样的引脚变形问题。该封装是美国 Motorola 公司开发的，首先在便携式电话等设备中被采用，今后在美国有可能在个人计算机中普及。最初，BGA 的引脚 (凸点)中心距为

Ebook--Low Power Methodology Manual[printable]

2007-12-11T23:40:00.001+08:00

Ebook share, Thanks to visit my blog! Low Power MethodologyManual For System-on-Chip Design. sorry, I can not share this book for some jural reason. if you are interesting with this book, you can refer http://www.synopsys.com/partners/arm/lpmm/lpmm.html

ECO Flow[By Nir Dahan]

2007-12-06T09:23:00.001+08:00

I have posted a blog about ECO some monthes ago, see http://www.yanzhi.org/blog/2007/04/eco.html And now it's another eco post from: Adventures in ASIC Digital Design , just for reference.ECO Flow By Nir Dahan Here is a useful checklist you should use when doing your ECOs. 1. RTL bug fix Correct your bug in RTL, run simulations for the specific test cases and some your general

What is the difference between hard macro, firm macro and soft macro?

2007-12-01T09:53:00.001+08:00

From http://vlsifaq.blogspot.com/ By murali What are IPs? Hard macro, firm macro and soft macro are all known as IP (Intellectual property). They are optimized for power, area and performance. They can be purchased and used in your ASIC or FPGA design implementation flow. Soft macro is flexible for all type of ASIC implementation. Hard macro can be used in pure ASIC design flow, not in FPGA

Physical Design Flow

2007-11-21T13:23:00.001+08:00

from ASIC-System On Chip (SoC)-VLSI Design by muraliLibrariesInputs–outputs from physical design processFloor PlanningPower PlanningTiming Analysis in Physical DesignPlacementClock Tree Synthesis (CTS)Routing

删除文本文件中包含特定字符串所在行[script tips]

2007-11-21T10:01:00.001+08:00

grep -v, --invert-match select non-matching lines grep -v "string" tee tmp.file mv -f tmp.file original.file Or vi :g/string/d

[转]What is the difference between FPGA and ASIC?

2007-11-20T16:25:00.001+08:00

from VLSI Interview Questions by muraliThis question is very popular in VLSI fresher interviews. It looks simple but a deeper insight into the subject reveals the fact that there are lot of thinks to be understood !! So here is the answer.FPGA vs. ASIC Difference between ASICs and FPGAs mainly depends on costs, tool availability, performance and design flexibility. They have their own pros and

a new gmail account for file sharing

2007-11-14T23:21:00.001+08:00

I have created a email account[gmail file sytem] for file sharing. account: share@ipcoretech.com password: ipcoretech.com address: http://mail.ipcoretech.com Powered By Gmail.com I have uploaded the "gmail driver" in it,and everyone can login and download it. Everyone can use this account by gmail dirver[maybe windows only] for sharing your files.

Google搜索在工作上的应用技巧[ 转]

2007-11-10T11:10:00.001+08:00

转自：http://www.williamlong.info/archives/572.html Google良好的搜索和易用性已经得到了广大网友的欢迎，但是除了我们经常使用的Google网站、图像和新闻搜索之外，它还有很多其他搜索功能和搜索技巧。如果我们也能充分利用，必将带来更大的便利。这里我介绍几个很有用的搜索技巧，在平时搜索中可以结合使用。　　一、限定搜索范围的技巧　　1、文件类型　　有时候我们可能不需要搜索网页文件或者图片，我们可能想要搜索其他类型的问题，比如文档文件（Word，Excel，PPT），Flash文件，甚至是Google地图文件，我们都可以使用"filetype"功能来实现。　　比如我想搜索一篇关于最新加密技术的Word论文，使用Google搜索"filetype:doc 加密技术 "即可得到大量相关信息。我想搜索关于中国的Google

blogspot又不能访问了

2007-11-10T09:16:00.001+08:00

很不幸blogspot又不能正常访问了，刚刚好了几天，我还以为以后都没问题了呢，还准备回归blogspot，看来还是不行更郁闷的是现在blogger的ftp发布也出现了问题，这段时间yanzhi.org/blog/的内容也不能正常显示了 -_-

New blog for backup

2007-11-06T20:40:00.000+08:00

I have build a new blog for this one's backup. http://digital-ic-design.blogspot.com/ And the new posts will be added at the same time from now on.

Some Testing Glossary

2007-11-05T13:40:00.001+08:00

[From http://digitalelectronics.blogspot.com/2007/10/some-testing-glossary.html ] Black box testing not based on any knowledge of internal design or code. Tests are based on requirements and functionality. White box testing based on knowledge of the internal logic of an application's code. Tests are based on coverage of code statements, branches, paths, conditions. Unit testing the most '

set false path

2007-11-01T10:37:00.001+08:00

A mistake in my work: In the synthesis script, we use the script below to set false path between each clock. set _all_clks [all_clocks];foreach_in_collection _clk $_all_clks { foreach_in_collection _other_clk [remove_from_collection $_all_clks $_clk] { set_false_path -from $_clk -to $_other_clk; }} However, there are two clocks with the same source(frenquence&phase) but different

Query Yourself before Architecting a Chip

2007-10-29T12:15:00.001+08:00

[From:http://www.vlsichipdesign.com/askyourselfarchitect.html] This article assuming you are an Architect and What all questions will come to your thought process before Architecting and making the Chip as a first-pass success. Chip Design is an Integration Challenge. What is the targetted market for this Chip. What are the competitor's to this Chip and Market Requirement and ROI What is the

On-Chip Variation(OCV) Analysis

2007-10-28T23:01:00.001+08:00

On Chip Variations or inter-die variations could be caused due to : • IR drop • Vt variations • Channel length variation So the normal flow of qualifying the Timing with plain worst and best corners is no more enough. Performing On-Chip Variation Analysis[From PrimeTime UG] To perform on-chip variation analysis, use the set_operating_conditions command. Because on-chip

Synopsys Design Compiler-A quick Tutorial

2007-10-17T21:04:00.001+08:00

From: http://www.vlsiip.com/dc_shell/ Step 0. Invoke Design Compiler unix> dc_shell-tStep 1. Setup technology library. To synthesize a design you need technology library which will contain description of the cells from the fab, and their timing. This is usually a .db file found in library installation directory. To do this 1(a). Tell synopsys where your .db

How to Get the Number of Gates in Design Compiler Synthesized Design

2007-10-17T09:14:00.001+08:00

set a 2-input NAND gate has an area of 1. dc_shell> get_attribute { tech_lib_name/2input_nand_gate_name } area

给数字IC设计新手入门的几点建议

2007-09-28T22:46:00.001+08:00

1.概念性的东西一点要弄明白，如一些基本的名词，简称等，养成搜索的习惯，通过这些关键字，慢慢就熟悉整个行业。建议碰到不熟悉的关键字，通过google，不但查到该词的意思，更要看与该词相关的一些内容。另外，给一个常用的查简称的网站， http://www.thefreedictionary.com/ ，我常用的办法是用"简称 + stand for"在google中搜索，一般最匹配的结果就是上面那个网站给的。 2.学习基本的HDL语言，FPGA设计流程和ASIC设计流程。做数字的话用HDL语言就好比建房子时的垒砖头，那些设计流程就好比按照房子的框架把砖头垒满，构成一间间的房屋。会了这几个东西就你就好比成了一个泥水匠。也许有人说建筑师不一定得从泥水匠开始做起，在现代社会分工这么明确，确实如此。不过我认为只有对底层的砖头的性能了解更清楚，才能造出最佳性能飞房屋。其中对于HDL语言的学习

How To Find All The High Fanout Nets In PrimeTime

2007-09-27T13:08:00.001+08:00

set high_fanout 2 set gan [get_nets -h *] foreach_in_collection gg $gan { set ggname [get_attribute $gg full_name] # echo "Processing $ggname" set gpins [get_pins -leaf -quiet -of $gg] set gpins_in [filter_collection $gpins "direction==in"] set gpins_in_soc [sizeof_collection $gpins_in] if { $gpins_in_soc > $high_fanout } { echo "Net $ggname is a high fanout net $gpins_in_soc

Handle Unconnected Pins in Design Compiler

2007-09-27T11:25:00.001+08:00

Question: The original Verilog code snippet is as follows: module sub ( C, z ); input C; output z; AN3 U1 ( .A(), .B(), .C(C), .Z(z) ); endmodule In the dumped Verilog, the code is as follows: module sub ( C, z ); input C; output z; AN3 U1 ( .A(1'b0), .B(1'b0), .C(C), .Z(z) ); endmodule Why does Design Compiler connect unconnected pins to 0? Answer: Because Design Compiler does not allow a